Physical layer devices, such as PHY-110 core, available from LSI Logic Corporation of Milpitas, Calif., output signals indicating the speed of operation, status of the link, activity, and the like. A system designer can use these signals to drive a display device such as light emitting diodes (LEDs) to monitor the device operation. In the case of a single port device, or a single-channel application, several (for example, four) signals are monitored and the corresponding number of output pins are assigned.
However, in a multiple-port device or a multiple-channel application, the number of the signal output pins is dramatically increased. For example, in a 12-port design the chip will need 48 signal pins (four pins per port) for just driving the LEDs. Since the chip must provide other pins for various interfaces (media interface, controller interface, management interface, scan interface, and the like), such a large number of monitoring pins is not desirable.
One conventional solution for the problem is to serialize the monitoring signals so as to reduce the pin number required for this function. That is, the information that was provided previously on separate pins is all sent serially as a stream to a single pin. Such a serial data stream is typically provided with a clock signal for timing and a latch enable signal for framing. Such signal serialization may be straightforward for a multiple port application where individual ports are not based on a single instance of the identical channel core.
However, in a multiple-port application where each port (or channel core) is a single instance of the identical port device (or channel core), serialization of the output signals is not so straightforward. Since each port may also be required to support a single-port application, the port level output signal is also serialized. Thus, in such a multiple-port design, each output signal from an individual port is already a serial data stream, which is timed by a clock signal and framed by its own latch enable signal.
FIG. 1 schematically illustrates a conventional multiple-port system 10 including a plurality of port devices 12. Each port device 12 is considered as a single instance of the identical port. Such a multiple-port system 10 may be implemented as an application specific integrate circuit (ASIC) or Application Specific Standard Product (ASSP), and typically used in a network interface chip or network interface card. Each port device 12 may be an individual channel core provided in a multiple-channel application of a system-on-chip design. Each port device 12 is supplied with a common clock signal (CLKI) and a common reset signal (RST). Other control signals, data signals, and the like (not shown) may also be supplied to each port device 12. Each port device 12 outputs a serial data stream (SLEDn), a clock signal (CLKOn), and a latch enable signal (LEn), where n=0, 1, . . . , N. Since the clock signal is common to all port devices, the output clock signals (CLKO) may be omitted from port devices except one.
Since each serial data stream is individually framed in a port device by a respective latch enable signal LE, although all of the port devices 12 simultaneously start timing the serial data streams (initiated by the reset signal), it is not guaranteed that these serial data streams remain synchronized in the course of operation. Once framing of the serial data stream is out of timing at one or more of the port devices due to noise, delay, and the like, there is no measure to recover synchronization. However, the synchronization across the data streams is required since an external device using this information expects all the serial data streams output from the multiple-pert system 10 to be synchronized. Therefore, it would be desirable to provide a scheme ensuring the synchronization across the serial data stream.